Lower Power - It’s all In the Architecture...

I was wandering around the show floor of the Design Automation Conference (DAC2009) in San Francisco last week talking to various vendors of EDA software and other interesting semiconductor design tools. I was amazed at how many vendors had that special tool for "lowering power by up to 20%" - just press the button and our tool will magically reduce your system power.  Oh, if it were only true - the problem is much deeper and complex than it appears.

We now live in a world where machines build machines - yes... it’s true... The Matrix is real - well, the "machines building machines" part anyway.  Ask a system-on-a-chip (SoC) designer to tell you exactly how his massive billion gate device works.  Not the blocks, inputs or outputs ("here we have a 128 bit bus for memory, and over here we have five megabytes of static ram, and here..."), but the real gates of the design at the transistor level.  This is like asking a software programmer to explain the machine code spit out of a C++ compiler - possible, but unlikely. 

These tools optimize and streamline the design based on embedded rules that are under the user’s control. They have limits in that the tool cannot improve an engineer’s bad design (software or otherwise).  So if engineers are trying to build lower power SoCs, then they need to use the most powerful tool available - the one between their ears. 

This is now a time when shrinking process geometries are causing new problems that are unlikely to go away with the next generation of tools.  When we were shrinking from 0.5 micron gate lengths to 0.35 micron lengths, problems with leakage and other structural artifacts were much easier to deal with.  Today, 45 nanometer gate lengths (0.045 micron - over 10x smaller) have an entire new set of problems.  First, there are a lot more transistors then when we were building chips from a 0.5 micron process. Second, they are running much faster and third, they leak current like a torpedoed ship leaks water - over three orders of magnitude higher than a typical 250 nm process (at 30 degrees C, 3000nA/um for a typical 45nm geometry process vs. 1nA/um for 250nm).

So what’s a designer to do to decrease power consumption?  Engineers need to start thinking of new ways to architect their designs. Here are some ideas:

1. Partition the system and provide isolation so that sections can be turned off.  Today’s tools allow for this, but very often engineers do not use this technique.

2. Don’t be afraid to provide multiple voltage islands.  Yes, it’s scary but foundries provide models of their processes at different operating points.  If you don’t need to go at warp 9.9, you don’t need your antimatter reactors running at full power... close your timing at the lower voltage and level shift that section.  Remember, dynamic power varies as the "square" of the supply voltage and leakage varies linearly as well...

3. Gate or dynamically scale your clocks.  If the system doesn’t need to be running at full speed, gate or slow down the clocks.  This is an architectural issue and some systems cannot utilize this method (e.g. video accelerators, etc.).  However, with some "re-thinking" there may be areas that can slow down at lighter loading or other conditions that do not require full performance.

4. Dynamically scale the supply voltage.  This can be done in combination with clock scaling and use either open loop table based methods such as Dynamic Voltage Scaling (DVS) or more advanced techniques such as Adaptive Voltage Scaling (AVS) which continuously monitors the process for adequate performance and automatically adjusts the supply voltage to maintain timing closure.

Any of these techniques will improve your power performance. So employ them - if not to save energy for the planet or reduce the system’s carbon footprint, then to save heat sinks or improve your mean time to failure numbers (lower junction temperature means longer life).  At this point, greater gains can be made by improving the architecture - at least until we make the move to quantum well transistors! Long live Moore’s Law...

Till next time...